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MPC2104P ? mpc2105p 1 motorola fast sram product preview 256kb/512kb burstram ? secondary cache modules for powerpc ? prep/chrp platforms the MPC2104P (256kb) and mpc2105p (512kb) are designed to provide burstable, high performance l2 cache for the powerpc 60x microprocessor family in conformance with the powerpc reference platform (prep) and the powerpc common hardware reference platform (chrp) specifications. the MPC2104P and mpc2105p utilize synchronous burstrams. the MPC2104P module is configured as 32k x 64 bits and uses two of the 3.3 v 32k x 32 data rams. the mpc2105p is configured as 64k x 64 bits and uses two of the 3.3 v 64k x 32 data rams. both modules are in a 178 (89 x 2) pin dimm format. for tag bits on the 2104p, a 5 v cache tag ram configured as 8k x 14 for tag field plus 8k x 2 for valid and dirty status bits is used. for tag bits on the 2105p, a 5 v cache tag ram configured as 16k x 14 for tag field plus 16k x 2 for valid and dirty status bits is used. bursts can be initiated with the ads signal. subsequent burst addresses are generated internally to the burstram by the cnten signal. write cycles are internally selftimed and are initiated by the rising edge of the clock (clkx) inputs. writes are global with two inputs for reduced loading. presence detect pins are available for auto configuration of the cache control. the module family pinout will support 5 v and 3.3 v components for a clear path to lower voltage and power savings. both power supplies must be connected. all of these cache modules are plug and pin compatible with each other. ? powerpcstyle burst counter on chip ? pipeline data i/o ? plug and pin compatibility ? multiple clock pins for reduced loading ? all cache data and tag i/os are lvttl (3.3 v) compatible ? three state outputs ? buffered addresses to data rams for reduced loading ? fast module clock rates: up to 66 mhz ? fast sram access times: 9 ns for tag ram match 8 ns for data ram ? decoupling capacitors for each fast static ram ? high quality multilayer fr4 pwb with separate power and ground planes ? 178 pin card edge module ? burndy connector, part number: elf178ksc3z50 burstram is a trademark of motorola. the powerpc name is a trademark of ibm corp., used under license therefrom. this document contains information on a new product under development. motorola reserves the right to change or discontinue this product without notice. order this document by MPC2104P/d semiconductor technical data MPC2104P mpc2105p rev 2 12/20/96 ? motorola, inc. 1996
MPC2104P ? mpc2105p 2 motorola fast sram MPC2104P block diagram 32k x 32 sram adsc adv sa1 ads0 sa0 sa a27 cwe0 a14 a26 sba sbd sw sgw pd3 pd2 pd1 pd0 j2 j0 j3 a14 a26 a0 a13 tclr twe clk2 match validin dirtyin tg tag: 16k x 14 + v + d a0 a12 reset tdq0 tdq13 tah, tag , tad sfunc, gs , a13 ws wt k validd dirtyd gt tt1, e1 e2, pwrdn v ss v cc via 100 w ta , validq v ccq v dd nc match dirtyout dirtyq j1 v cc v cc v dd zz g v dd se1 k cg0 dh0 dh31 standby burstmode clk0 se3 lbo dqa dqd se2, adsp a28 cnten0 v ss v ss v dd via 100 w v dd clk1 v ss v dd via 100 w v dd 16244 32k x 32 sram adsc adv sa1 sa0 sa cwe1 sba sbd sw sgw v dd zz g se1 k dl0 dl31 standby burstmode se3 lbo dqa dqd se2, adsp v dd 22 w 22 w 22 w
MPC2104P ? mpc2105p 3 motorola fast sram mpc2105p block diagram pd3 pd2 pd1 pd0 j2 j0 j3 a13 a26 a0 a12 tclr twe clk2 match validin dirtyin tg tag: 16k x 14 + v + d a0 a13 reset tdq0 tdq12 tah, tag , tad sfunc, gs ws wt k validd dirtyd gt tt1, e1 e2, pwrdn v ss v cc via 100 w ta , validq v ccq v dd nc match dirtyout dirtyq j1 v cc v cc tdq13 v ss 4.7k w 64k x 32 sram adsc adv sa1 ads0 sa0 sa a27 cwe0 a13 a26 sba sbd sw sgw v dd zz g v dd se1 k cg0 dh0 dh31 standby burstmode clk0 se3 lbo dqa dqd se2, adsp a28 cnten0 v ss v ss v dd via 100 w v dd clk1 v ss v dd via 100 w v dd 16244 64k x 32 sram adsc adv sa1 sa0 sa cwe1 sba sbd sw sgw v dd zz g se1 k dl0 dl31 standby burstmode se3 lbo dqa dqd se2, adsp v dd 22w 22w 22w
MPC2104P ? mpc2105p 4 motorola fast sram pin assignment 178lead dimm pin name pin name pin name pin name pin name pin name pin name 1 v ss 27 dh0 53 dl1 79 v ss 105 dh14 131 dl17 157 a22 2 pd0/idsclk 28 nc 54 dl0 80 a7 106 dh13 132 nc 158 a20 3 pd2 29 v ss 55 v ss 81 a5 107 nc 133 dl15 159 v ss 4 dh30 30 clk1 56 clk2 82 a3 108 dh10 134 dl13 160 a18 5 dh28 31 v ss 57 v ss 83 a0 109 dh8 135 v ss 161 a16 6 dh26 32 dl28 58 nc 84 v cc 110 nc 136 dl10 162 a15 7 dh24 33 dl26 59 cg0 85 tclr 111 dh6 137 dl8 163 a14 8 v dd 34 dl24 60 nc 86 match 112 v dd 138 cwe1 164 v dd 9 nc 35 nc 61 v dd 87 tg 113 dh4 139 dl6 165 a10 10 dh22 36 nc 62 nc 88 dirtyin 114 v ss 140 v dd 166 a8 11 dh20 37 dl22 63 reserved 89 v ss 115 clk0 141 dl5 167 a6 12 dh19 38 dl20 64 ads0 90 v ss 116 v ss 142 dl2 168 v ss 13 v ss 39 dl18 65 nc 91 pd1/idsdata 117 dh1 143 v ss 169 a4 14 dh17 40 dl16 66 a28 92 pd3 118 nc 144 nc 170 a2 15 nc 41 v ss 67 a26 93 dh31 119 dl31 145 v ss 171 a1 16 dh15 42 nc 68 a25 94 dh29 120 dl30 146 nc 172 burstmode 17 dh12 43 dl14 69 a23 95 dh27 121 v ss 147 v ss 173 v cc 18 nc 44 dl12 70 v ss 96 dh25 122 dl29 148 cwe0 174 validin 19 dh11 45 dl11 71 a21 97 v dd 123 dl27 149 nc 175 twe 20 dh9 46 v ss 72 a19 98 nc 124 dl25 150 v dd 176 standby 21 nc 47 dl9 73 a17 99 dh23 125 nc 151 nc 177 dirtyout 22 dh7 48 nc 74 a13 100 dh21 126 nc 152 reserved 178 v ss 23 v dd 49 dl7 75 v dd 101 dh18 127 dl23 153 cnten0 24 dh5 50 dl4 76 a12 102 v ss 128 dl21 154 nc 25 dh3 51 v dd 77 a11 103 dh16 129 dl19 155 a27 26 dh2 52 dl3 78 a9 104 nc 130 v ss 156 a24 note: v cc and v dd must be connected on all modules. top view case tbd 1 42 43 89 90 131 132 178 65 154 66 155
MPC2104P ? mpc2105p 5 motorola fast sram pin descriptions pin locations symbol type description 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 a0 a28 input address inputs e (msb:0, lsb:28). 64 ads0 input data ram address strobe. 172 burstmode input burstmode. 0 = linear, 1 = interleaved. 59 cg0 input data ram output enable. 30, 56, 115 clk0 clk2 input clock inputs e clk2 is for tag ram, clk0 and clk1 are for data rams only. 153 cnten0 input data ram count enable. 138, 148 cwe0 cwe1 input data ram write enables e (msb:0, lsb:1). 4, 5, 6, 7, 10, 11, 12, 14, 6, 17, 19, 20, 22, 24, 25, 26, 27, 93, 94, 95, 96, 99, 100, 101, 103, 105, 106, 108, 109, 111, 113, 117 dh0 dh31 i/o high data bus e (msb:0, lsb:31). 88 dirtyin input dirty input bit. 177 dirtyout output dirty output bit. 32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 119, 120, 122, 123, 124, 127, 128, 129, 131, 133, 134, 136, 137, 139, 141, 142 dl0 dl31 i/o low data bus e (msb:0, lsb:31). 86 match output tag ram active high match indication. 2 pd0/idsclk input presence detect bit 0/eeprom serial clock. (eeprom option only). 91 pd1/idsdata i/o presence detect bit 1/eeprom serial data. (eeprom option only). 3, 92 pd2, pd3 output presence detect bits. 63, 152 reserved reserved pin. 176 standby input standby pin. reduces standby power consumption. 85 tclr input tag ram clear. 87 tg input tag ram output enable. 175 twe input tag ram write enable. 174 validin input tag ram valid bit. 84, 173 v cc input + 5 v power supply. must be connected. 8, 23, 51, 61, 75, 97, 112, 140, 150, 164 v dd input + 3.3 v power supply. must be connected. 1, 13, 29, 31, 41, 46, 55, 57, 70, 79, 89, 90, 102, 114, 116, 121, 130, 135, 143, 145, 147, 159, 168, 178 v ss input ground. 9, 15, 18, 21, 28, 35 36, 42, 48, 58, 60, 62, 65, 98, 104, 107, 110, 118, 125 126, 132, 144, 146, 149, 151, 154 nc e there is no connection to the module.
MPC2104P ? mpc2105p 6 motorola fast sram truth table (see notes 1 through 4) next cycle address used standby ads0 cnten0 cg0 2 dhx/dlx cwex 2 deselect none 1 0 x x highz x begin read external 0 0 x x highz 1 4 continue read next x 1 0 1 highz 1 continue read next x 1 0 0 dq 1 suspend read current x 1 1 1 highz 1 suspend read current x 1 1 0 dq 1 begin write external 0 0 x x highz 0 continue write next x 1 0 x highz 0 suspend write current x 1 1 x highz 0 notes: 1. x = don't care. 1 = logic high. 0 = logic low. 2. cg0 is an asynchronous signal and is not sampled by the clock clk0. cg0 drives the bus immediately (t glqx ) following cg0 going low. 3. on write cycles that follow read cycles, cg0 must be negated prior to the start of the write cycle to ensure proper write data setup times. cg0 must also remain negated at the completion of the write cycle to ensure proper write data hold times. 4. this read assumes the ram was previously deselected. asynchronous truth table operation cg0 i/o status read l data out (dhx/dlx) read h highz write x highz deselected x highz sleep x highz linear burst address table (burst mode = v ss ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10 interleaved burst address table (burst mode = v dd ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00
MPC2104P ? mpc2105p 7 motorola fast sram absolute maximum ratings (voltages referenced to v ss = 0 v) rating symbol value unit power supply voltage tag data ram v cc v dd 0.5 to + 7.0 0.5 to + 4.6 v voltage relative to v ss tag data ram v in , v out 0.5 to v cc + 0.5 0.5 to v dd + 0.5 v output current (per i/o) tag data ram i out 20 30 ma power dissipation p d 3.86 w temperature under bias t bias 10 to + 85 c operating temperature t a 0 to +70 c storage temperature t stg 55 to + 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. dc operating conditions and characteristics (v cc = 5.0 v 5%, v dd = 3.3 v + 10%, 5%, t a = 0 to + 70 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min max unit supply voltage (operating voltage range) v cc v dd 4.75 3.135 5.25 3.60 v input high voltage v ih 2.2 v dd + 0.3** v input low voltage v il 0.5* 0.8 v *v il (min) = 0.5 v dc; v il (min) = 2.0 v ac (pulse width 20 ns) for i 20.0 ma. ** v ih (max) = v dd + 0.3 v dc; v ih (max) = v dd + 2.0 v ac (pulse width 20 ns) for i 20.0 ma. dc characteristics parameter symbol min max unit input leakage current (all inputs, v in = 0 to v dd ) i lkg(i) e 1.0 m a output leakage current (cg = v ih , v out = 0 to v dd ) i lkg(o) e 1.0 m a ttl output low voltage (i ol = + 8.0 ma) v ol e 0.4 v ttl output high voltage (i oh = 4.0 ma) v oh 2.4 e v power supply currents parameter symbol max unit ac supply current (cg = v ih , e = v il , i out = 0 ma, all inputs = v il and v ih , MPC2104P v il = 0.0 v and v ih 3.0 v, cycle time 20 ns) mpc2105p i dda 410 700 ma i cca 320 ma ac standby current (e = v ih , i out = 0 ma, all inputs = v il or v ih MPC2104P v il = 0.0 v and v ih 3.0 v, cycle time 20 ns) mpc2105p i sb1 (v dd ) 210 240 ma i sb1 (v cc ) 320 ma capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 25 c, periodically sampled rather than 100% tested) parameter symbol max unit input capacitance (a13 a28) (data ram control pins) (clk0 clk2) (tag control pins) c in 15 10 5 5 pf tag output capacitance (match, dirtyout) c out 7 pf data ram input/output capacitance (dh0 dh31, dl0 dl31) c i/o 8 pf tag input/output capacitance (a0 a11) c i/o 7 pf this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up.
MPC2104P ? mpc2105p 8 motorola fast sram data rams ac operating conditions and characteristics (v cc = 5.0 v 5%, v dd = 3.3 v + 10%, 5%, t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 1a unless otherwise noted . . . . . . . . . . . . . synchronous data rams read/write cycle timing (see notes 1 and 2) p sbl MPC2104P/5p ui n parameter symbol min max unit notes cycle time t khkh 15 e ns clock access time t khqv e 8 ns 3 output enable to output valid t glqv e 6 ns clock high to output active t khqx1 0 e ns clock high to output change t khqx2 2 e ns output enable to output active t glqx 0 e ns output disable to q highz t ghqz e 8 ns clock high to q highz t khqz 2 8 ns clock high pulse width t khkl 5 e ns clock low pulse width t klkh 5 e ns setup times: address address status data in write address advance chip enable t avkh t svkh t dvkh t wvkh t bavvkh t evkh 2.5 e ns 4 hold times: address address status data in write address advance chip enable t khax t khtsx t khdx t khwx t khbax t khex 0.5 e ns 4 notes: 1. all read and write cycle timings are referenced from clk or cg0 . 2. cg is a don't care when cwe x is sampled low. 3. maximum access times are guaranteed for all possible powerpc external bus cycles. 4. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk whenever ads0 is low, and the chip is selected. all other synchronous inputs must meet the specified setup and hold times for all rising edges of clk when the chip is enabled. chip enable must be valid at each rising edge of clock for the device (when ads0 is low) to remain enabled.
MPC2104P ? mpc2105p 9 motorola fast sram burst read single read ads0 t khkl t khkh dqx standby clkx cnten0 q(a) burst write a14 a26 ab read/write cycles t klkh cd cwex q(b) q(b+1) t khqv q(b+2) q(b+3) d(c) d(c+1) d(c+2) d(c+3) d(d) t khqv deselected single coe0 t khqx1 t khqx2 t ghqz q(n1) t khqz write
MPC2104P ? mpc2105p 10 motorola fast sram tag ram reset function truth table (see notes 1 and 2) tclr clk twe tag0 tag11 dirtyout match operation power l l h h highz l (3) l (3) reset status active l l h l e e e not allowed e notes: 1. h = v ih , l = v il , x = don't care, e = undefined. 2. tg is x for this table. 3. these are output states. read function truth table (see notes 1, 2, and 3) tg twe clk tag0 tag11 validin dirtyin dirtyout match operation l h x d out e e d out d out read tag i/o h x x highz e e e e tag i/o disable write function truth table (see notes 1 and 2) tg twe clk tag0 tag11 validin dirtyin dirtyout match operation h l l h d in e e e l write tag i/o l l l h e e e e e not allowed notes: 1. h = v ih , l = v il , x = don't care, e = undefined. 2. this table applies when reset and pwrdn are high. 3. d out in this case is the same as d in . the input data is written through to the outputs during the write operation. match function truth table (see notes 1 through 4) tg twe tag0 tag11 validin (4) dirtyin (4) match operation x x e e e d out selected l h d out e e l read tag i/o h l d in d in d in l write tag i/o, status bits h h tag in l e l invalid data e dedicated status bits h h tag in h e h match e dedicated status bits notes: 1. h = v ih , l = v il , x = don't care, e = undefined. 2. m = high if tag in equals the memory contents at the address; m = low if tag in does not equal the contents at that address. 3. pwrdn and reset are high for this table. gs and clk are x. 4. this column represents the stored memory cell data for the given status bit at the selected address.
MPC2104P ? mpc2105p 11 motorola fast sram tag ram ac operating conditions and characteristics (v cc = 5.0 v 5%, t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing measurement reference level 1.5 v . . . . . . . . . . . . . output load figure 1a unless otherwise noted . . . . . . . . . . . . . . . . . tag ram read cycle (see notes 1 through 4) p sbl tag ram ui parameter symbol min max unit clock access time t khqv e 10 ns output enable to output valid t glqv e 8 ns output enable to output active t glqx 0 e ns output disable to q highz t ghqz 1 6 ns status bit hold from address change t axsx 3 e ns address access time status bits t avsv e 10 ns tag bit hold from address change t avqx 3 e ns address access time tag bits t avqv e 12 ns notes: 1. setup and hold times, w (write) refers to twe . 2. a read cycle is defined by twe high. a write cycle is defined by twe low. 3. maximum access times are guaranteed for all possible mc68040 and powerpc external bus cycles. 4. tag reads are asynchronous. tag ram write cycle (see notes 1 through 4) p sbl tag ram ui parameter symbol min max unit cycle time t khkh 15 e ns clock high pulse width t khkl 4.5 e ns clock low pulse width t klkh 4.5 e ns clock high to output active t khqx 1.5 e ns setup times address write t avkh t wvkh 3 e ns hold times address write t khax t khwx 1.5 e ns status output hold t khsx 0 e ns clock high to status bits valid t khsv e 9 ns notes: 1. setup and hold times, w (write) refers to twe . 2. a read cycle is defined by twe high. a write cycle is defined by twe low. 3. maximum access times are guaranteed for all possible mc68040 and powerpc external bus cycles. 4. tag writes are synchronous.
MPC2104P ? mpc2105p 12 motorola fast sram tag ram write and read cycles clk a14 a26 twe a0 a13 tg valid valid valid valid input valid output valid output valid output valid valid valid valid valid t avkh t khax status write tag read tag write after read t wvkh t khwx t wvkh t khwx t khsv t khsx t wvkh t khwx t khqv t khqx t avsv t ghqz t glqx t axsx validin dirtyin dirtyout t khkl t klkh t khkh t glqv t avqv t axqx t avkh t khax (see note 1) (see note 1) t avsv t axsx notes: 1. transition is measured plus or minus 200 mv from steady state. 2. tclr = high. tag read after write (see note 2)
MPC2104P ? mpc2105p 13 motorola fast sram tag ram match cycle p sbl tag ram ui parameter symbol min max unit clock high write to match invalid t khml e 7 ns clock high read to match valid t khmv e 10 ns address valid to match valid t avmv e 10 ns match valid hold from address change t axmx 2 e ns tg low to match invalid t glml e 7 ns tg high to match valid t ghmx e 8 ns tag ram reset (tclr ) cycle p sbl tag ram ui parameter symbol min max unit tclr setup time t stc 4 e ns tclr hold time t htc 1 e ns status bit reset time t srst e 60 ns status bit hold from tclr low t shrs 2 e ns tclr low to match invalid t rsml e 10 ns tclr high to match valid t rsmv e 100 ns tclr low to tag highz t rsqz e 10 ns tclr high to tag active t rsqx e 100 ns standby setup to tclr low t pdsr 30 e ns tclr high to twe low t rhwx 80 e ns output z 0 = 50 w 50 w v l = 1.5 v (a) (b) 5 pf +5 v output 255 w 480 w timing limits the table of timing values shows either a minimum or a maximum limit for each param- eter. input requirements are specified from the external system point of view. thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time. on the other hand, responses from the memory are specified from the de- vice point of view. thus, the access time is shown as a maximum since the device never provides data later than that time. figure 1. test loads
MPC2104P ? mpc2105p 14 motorola fast sram match clk a14 a26* tag ram match cycle valid match valid valid t avmv t axmx t khwx t khwx t wvkh t wvkh t wvkh twe a0 a13 tg valid address valid match data from: processor processor tag ram valid t glml t glmx t khml t khmv *cache addresses used are: a14 a26 for MPC2104P.
MPC2104P ? mpc2105p 15 motorola fast sram match clk t htc tag ram tclr function * transition is measured plus or minus 200 mv from steady state. t rsqx t srst t stc t wvkh t rsqz* t rhwx a0 a13 twe dirtyout tclr valid t shrs t rsmv ordering information (order by full part number) 2104p mpc 2105p xx xx motorola memory prefix part number full part numbers e MPC2104Pdg66 MPC2104P = 256kb, synchronous pipelined mpc2105pdg66 mpc2105p = 512kb, synchronous pipelined speed (66 = 66 mhz) package (dg = gold pad dimm)
MPC2104P ? mpc2105p 16 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405, denver, colorado, 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com e touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 MPC2104P/d ?

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